Appendix 2.1 to ETSO-C153a - Integrated Modular Avionics (IMA) Module Minimum Performance Standard (MPS)

• ED Decision 2020/011/R found in: CS-ETSO Amdt 17 - European Technical Standard Orders (Oct 2026)

**Appendix 2.1 to ETSO-C153a – Integrated Modular Avionics (IMA) Module Minimum Performance Standard (MPS)** *ED Decision 2020/011/R* **COMMON: Applicable to all IMA modules** **1. Purpose and scope** This Appendix contains a set of Minimum Performance Standards (MPS) applicable to any IMA module and to any implemented intended function class(es). In the following, the term ‘concurrent items’ designates the items (applications, for example) that use the shared resource of the IMA module. Depending on the module class, it means ‘processing element’ for PR class, ‘thread’ for GP, IF and DH class, ‘data storage element’ for DS class, and ‘power rail’ for PS class. **2. Requirements** 2.1. Functional requirements common to all classes CO.a) The IMA shall implement at least one Function Class. The following requirements of this paragraph are applicable to all classes with some exception as described below: CO.b) Except for the housing function (F1) of class RH (see Appendix 2.2, paragraph  2.1.1), the IMA module shall provide at least the following control features to react to detected failures: a. disable, and b. reset. CO.c) Except for the Housing function (F1) of class RH (see Appendix 2.2, paragraph 2.1.1), each IMA module shall provide a health management and reporting capability. CO.d) Except for the housing function (F1) of class RH (see Appendix 2.2 , paragraph 2.1.1), the health management and reporting function shall detect, isolate, contain and report faults (in the shared resources and other resources) that could adversely affect applications using the module resources or the resources themselves. CO.e) Except for class RH, robust partitioning (as per EUROCAE ED-124/RTCA DO-297) between ‘concurrent items’ sharing the resource shall be ensured by the IMA module. CO.f) Except for class RH, robust partitioning shall not rely on any required behaviour of any aircraft function or hosted application (as per EUROCAE ED-124/RTCA DO-297, Section 3.5c). CO.g) Except for class RH, the potential breaches in robust partitioning shall be identified. An appropriate process and means should be implemented to ensure that such failures which result or may result in an unsafe condition are detected and reported. CO.h) Except for class RH, the IMA module shall implement a fault containment mechanism to prevent fault propagation between ‘concurrent items’ using the shared-resource elements and between other IMA modules. CO.i) Reserved. CO.j) Except for the housing function (F1) of class RH (see Appendix 2.2, paragraph 2.1.1), the interface between the ‘concurrent items’ and the shared resource should conform to the characteristics as described by a standard (ARINC specifications 653, 664, and 600, for example). 2.2. Characterisation requirements CO.k) Each item of the characterisation shall be documented in the User Guide/Installation Manual as appropriate. CO.l) The IMA module specification shall be characterised based on items in the table below (Figure 4: IMA module Characterisation Categories) and on the characterisation requirements identifying additional characterisation items specific to each functional class (defined in Appendix 2 — Class RH, PR, GP, DS, IF, PS, and DH). CO.m) Quantifiable characterised items shall be quantified in terms of minimum, typical (when relevant) and maximum values and the associated accuracy. Note: The influence of environmental or abnormal conditions should be considered when relevant. CO.n) The characterisation of the IMA module shall be correct and complete. Completeness is achieved when all the shared features of the IMA module have been characterised. CO.o) The characterisation shall identify the valid usage domain of the IMA module. CO.p) The characterisation shall provide all constraints on the usage domain and on the installation (including limitations and activities) to be respected by the users. CO.q) The characterisation shall provide the list of types of shared-resource elements, the associated attributes, their configurability and their performances, and their associated limit of use. CO.r) The characterisation shall include at least the following characteristics of the core software/programmable hardware: a. the identification of the core software component(s)/programmable hardware (if any); b. the IMA module functionality, performance and safety requirements supported by the core software/programmable hardware; c. external interfaces and associated data coupling/control-coupling information; d. integration and loading procedure(s); and e. the development assurance level(s). CO.s) When the IMA module offers the capability to host software, the characterisation shall provide any data needed to evaluate the worst-case execution time (WCET) of each concurrent item sharing the IMA module resource. CO.t) The performances of each shared-resource management mechanism including monitoring shall be characterised, in particular the range, timing aspects, transients, etc. CO.u) For at least the following failure modes, the failure rate shall be provided: a. a loss of the IMA module; b. erroneous behaviour of the IMA module; c. a loss of the shared-resource element; and d. erroneous behaviour of the shared-resource element. CO.v) The characterisation shall include the monitoring coverage rate (PBIT, CBIT, etc.) for the identified failure modes of the IMA module (including shared and unshared resources, sharing mechanisms and robust partitioning mechanisms). CO.w) The characterisation shall address the safety aspects of bad sequencing, delay, corruption and impersonation, where applicable. CO.x) The following health monitoring items shall be included in the characterisation: a. interface rules, constraints (including limitations) to be respected by the users; b. list of Health Monitoring services; c. list of monitored components, monitored services, monitored interfaces; d. response to each type of fault; e. fault reporting attributes (reporting refers to internal logging, indication to applications using the shared resources, indication outside of the module); and f. the configuration attributes, if any. CO.y) If the IMA module is configurable, the characterisation shall include, in addition, the following items: a. the authorised configuration parameters (including range, type and definition of combined parameters) in the usage domain; and b. the configuration activities to be conducted (including configuration procedures, means and tools) by the user during application development (EUROCAE ED-124 — Task 2) and IMA system integration (EUROCAE ED-124 — Task 3 and 4). CO.z) If some tools are required for installation, these tools shall be characterised according to the following: a. identification; b. the user’s manuals of the tools; c. the activities related to those tools to be conducted during application development (EUROCAE ED-124 — Task 2) and IMA system integration (EUROCAE ED-124 — Task 3 and 4); d. the proposed associated qualification credits that could be granted to the user of the tools; e. the category of the tool and the Development Assurance Level of the tool (if any) as defined in the applicable Software Development assurance guidance (see Section 2.2 of CS-ETSO, Subpart A,); and f. limitations and Open Problem Report (if any) on tools that could affect the tool qualification credit and require analysis by the user. CO.aa) The compatibility and mixability information between hardware, software, tools and usage domain shall be part of the characterisation. This characterisation shall address at least the following: a. how the authorised mixed combinations are verified; b. the compatibility assessment process with authorised mixed combinations of interfacing modules (external mixability); c. any preventative measures (design or procedures) to be developed by the user to prevent incorrect module combinations or software loads; and d. information to be provided to maintenance personnel. CO.bb) The control features (disable, reset, reload, etc.) of the IMA module for reacting to detected failures shall be characterised. <table bgcolor="#d9d9d9" cellpadding="7" cellspacing="0"> <col/> <col/> <thead> <tr valign="top"> <td bgcolor="#808080"><p align="left"> Characterisation Category</p> </td> <td bgcolor="#808080"><p align="left"> Characterisation item</p> </td> </tr> </thead> <tbody> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="left"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="left"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9" rowspan="20"><p align="left"> General Information</p> </td> <td bgcolor="#d9d9d9"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Power Dissipation</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Thermal characteristics</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Temperature control (e.g. cooling) characteristics</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Size and Weight</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input and Output (I/O) Connectors (including pinout)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Mating Connectors</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Top-level drawings and Mechanical Interfaces</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Mounting Mechanism and scheme</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Clearance characteristics</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Air Flow characteristics</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Inter-Element Interfaces (such as Backplane interface)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Grounding and Shielding Provisions</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Separation and/or Isolation Provisions</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Module Installation and Extraction Means</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Backplane Interface</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Start-up sequence</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Different operational modes (initialisation, monitor, operational etc.)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9" rowspan="72"><p align="left"> Interfaces</p> </td> <td bgcolor="#d9d9d9"><p align="left"> <b>Analogue Input Specifications For Each Analogue Input</b></p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Type of Analogue (e.g. differential, isolated, etc.)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Range</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Accuracy</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Resolution</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Null and Offset</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Filtering</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Analogue-to-Digital Conversion Speed</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Steady-State Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Transient Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Multiplexing</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Latency Time</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Bandwidth</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <b>Analogue Output Specifications For Each Analogue Output</b></p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Type of Analogue (e.g. differential, isolated, etc.)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Range</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Accuracy</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Null</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Linearity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Current Capacity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Output Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Steady-State Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Transient Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Multiplexing</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Latency Time</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Bandwidth</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <b>Discrete Input Specifications For Each Discrete Input</b></p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Trip Point</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Hysteresis</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Filtering</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Logic Sense</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Maximum Logic–High Level</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Maximum Logic–Low Level</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Minimum Logic–High Level</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Minimum Logic–Low Level</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Steady-State Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Transient Voltage Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Multiplexing</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <b>Discrete Output Specifications For Each Discrete Output</b></p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Voltage Levels</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Current Source Capacity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Current Sink Capacity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Output Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Multiplexing</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <b>Digital Communications For Each Input and Output</b></p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Data Rates</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Integrity Checks</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Signal Levels</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Current Sink and Source</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Output Impedance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Signal Rise and Fall Times</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Filtering</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Stub Length Limits</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input and Output Capacitance</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Isolation</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Maximum Bit Error Rates</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Resets</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Monitors</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Multiplexing</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9" rowspan="7"><p align="left"> Processing and Memory (inc. Graphical)</p> </td> <td bgcolor="#d9d9d9"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Included Software Services (Core Software) and associated performances: Data loading, Health Management, Operating System</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Processing Unit (CPU, GPU, etc.), Component(s), Bus(es) and Core Clock Frequencies</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Memory Size(s), Type(s), Control of Access and Timing(s)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Local data bus(es) Type(s) and Timings</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Start-up and Reset mechanisms and timings</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9" rowspan="3"><p align="left"> Display and Rendering</p> </td> <td bgcolor="#d9d9d9"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Refer to SAE AS8034 ‘Minimum Performance Standard for Airborne Multipurpose Electronic Displays’ (revision as defined in the applicable release of ETSO-C113)</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9" rowspan="12"><p align="left"> Power Supply</p> </td> <td bgcolor="#d9d9d9"><p> <br/> </p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Regulation</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Input Voltage and Current range</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Maximum Start-up (Input and Output Inrush) Current Rating</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Hold-up Capacity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Restart</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Transient Immunity</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Short Circuit Management</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Power Resets and Recovery</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Circuit Protection Techniques</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> Slew rate at start-up</p> </td> </tr> <tr> <td bgcolor="#d9d9d9" valign="top"><p align="left"> <br/> </p> </td> </tr> </tbody> </table> ***Figure 4: IMA module Characterisation Categories*** The following list of terms summarises the terminology used in the characterisation items defined in Figure 4 that are applicable to this ETSO, in the development of hardware elements, and in the application of the Appendix 1 MPS development criteria. The terms are segregated into eight categories according to the performance of the appropriate hardware element. (1) General Terms **Air Flow Characteristic:** specific requirements to provide air movement into or onto a cabinet, LRU, or module (e.g. air temperature, volume rate, and pressure). **Analogue/Digital Conversion Speed:** the time to perform one Analogue-to-Digital (A-to-D) conversion. Typically, this is expressed as either the time for one analogue conversion performed by the A/D converter device or the frequency at which all analogue inputs are converted. **Circuit Protection Techniques:** the electrical isolation or circuitry included in inputs or outputs to protect the functional circuits from external environments(for example solutions to protect circuits from the indirect effects of lightning). **Current Source/Sink:** the maximum current drawn by the output while pulling the signal to a zero-volt (ground) level. **Current Source:** the maximum current supplied by the output while driving the signal to a voltage level. **Clearance Characteristics:** additional spacing requirements in specific directions from the cabinet or rack beyond the outline dimensions (e.g. additional clearance is the area to allow proper airflow). **Design Assurance:** all planned and systematic actions and data used to substantiate that hardware correctly performs its intended function(s) and that design errors have been identified and corrected such that the hardware satisfies the applicable certification basis. **Development Assurance:** all planned and systematic actions and data used to substantiate that the system performs its intended function(s) and that development errors have been identified and corrected such that the system satisfies the applicable certification basis. **Functional Software:** software applications that will be approved as part of a functional TSO authorisation or as part of a type certification effort. This software is sometimes referred to as operational software, application software, or flight software. **Functional ETSO:** an ETSO with defined functionality (for example, Airborne Weather Radar, ETSO-C63). ETSO-C153a is not considered a functional ETSO, because IMA hardware elements typically do not have system-level functionality. **Grounding/Shielding Provisions:** the electrical and/or mechanical details of the design which provide grounding of the element or shield connections. These are the design details usually associated with the Radio Frequency emission and susceptibility protection of the system. **Hardware element:** in this ETSO, a hardware element is (1) a hardware module, or (2) cabinets or racks that host hardware modules. Note: This definition may differ from the terminology used in other documents (e.g. ED-80/RTCA DO-254). **Inter-Element Connections:** the connector type specification and connector pin assignments specified to allow modules to be installed interchangeably in the cabinets or racks. **Inter-Element Interfaces:** the definition of the electrical signals, timing requirements, and protocols used to communicate among modules or elements with the cabinet or system. **Module Extraction Means:** the details of the mechanical design to enable removal of the module from the cabinet. **Module Mounting Scheme:** the details of the mechanical design used to secure each module into the cabinet or rack. **Mounting Mechanism:** the details of the mechanical mechanism(s) used to secure the module into the cabinet or rack of the aircraft. **Multiplexing:** the design technique where multiple inputs are individually switched to one receiver (for example, multiple digital communication buses switched to a serial receiver) or multiple outputs are individually supplied by the same circuit (for example, multiple analogue outputs driven by one Digital-to-Analogue converter through multiple sample-and-hold). **Separation/Isolation Provisions:** the electrical and/or mechanical details of the design which provide physical or electrical means of reducing interference from one element to another. **Steady State Voltage Rating:** the maximum voltage range that can be applied continuously to an input or output without resulting in damage. **Transient Voltage Rating:** the maximum voltage that can be applied for a short period of time to an input or output without resulting in damage. The maximum duration of the transient must be included. (2) Analogue Input/Output Terms **Accuracy:** the degree of conformity to the true value of the signal. This is usually expressed as a percentage of the reading or a percentage of the full-scale value of the signal. **Current Capacity:** the maximum amount of current that can be sinked or sourced by the circuit. **Linearity:** the error from the directly proportional expected signal value as the signal values vary over the entire range. **Null:** the signal value(s) for which a value of zero is identified. This is usually shown as positive and negative voltage values. **Offset:** the indicated signal value (usually non-zero) when zero volts are applied. Range: the least and greatest operating voltage extremes (full scale) of the signal; the voltage extremes between which the signal value is valid. **Resolution:** the smallest measurable division of the numerical expression of the signal. This is usually identified as the number of binary bits used to express the signal value and/or the value in volts of the least significant binary bit (LSB). (3) Discrete Input/Output Terms **Discrete Input:** this is an input with only two states. Typical examples are ‘ground or open’ and ’28-volt and open’ inputs. **Discrete Output:** this is an output with only two states. Typical examples are ‘ground or open’ and ’28-volt and open’ outputs. (4) Input Terms **Hysteresis:** the value of the input voltage lag when changing states. For example, if an input circuit has 0.2 volts of hysteresis and if the trip point is 2.0 volts, then the circuit will change state as the input voltage reaches 2.0 volts but will not revert back to the original state until the input voltage drops below 1.8 volts. **Logic Sense**: this is the functional interpretation of the discrete input states. A true or positive logic sense may identify the ‘ground’ state as ‘low’ or binary ‘0’. An inverse or negative logic sense may identify a ‘ground’ state as ‘high’ or binary ‘1’. **Maximum Logic–High Level**: the largest voltage value that can be applied to the input and that the circuit will interpret as ‘high’. **Maximum Logic–Low Level**: the largest voltage value that can be applied to the input and that the circuit will interpret as ‘low’. **Minimum Logic–High Level**: the smallest voltage value that can be applied to the input and that the circuit will interpret as ‘high’. **Minimum Logic–Low Level**: the smallest voltage value that can be applied to the input and that the circuit will interpret as ‘low’. **Trip Point**: this is the input voltage value at which the input circuitry changes state. (5) Output Terms **Current Sink Capacity:** the maximum current by the output while pulling the signal to a zero-volt (ground) level (current flowing in the direction from the load to the element output). **Current Source Capacity:** the maximum current supplied by the output while driving the signal to a voltage level (current flowing from the element output to the load). **Voltage Levels:** the minimum and maximum voltages for each state of the output. The ground point that is to be used as reference must be identified. (6) Processor Terms **Backplane Interface:** the definition of the electrical signals, buses, timing requirements, and protocols used to communicate among elements installed in a cabinet or rack. **Interrupts:**the signals to the processor that stops execution of an ongoing process or application. These signals indicate that there is a higher priority request of task or that an asynchronous event is occurring. **Memory Management Unit:** a specialised control circuitry, sometimes integrated within the microprocessor, which performs predictive reads of instruction (prefetch) for use by the processor. It also may perform structured or prioritised control of specific sections of the memory. **Monitors:** specific circuits which observe the normal operation of the processing system and alert the processor or user to an abnormal condition. Examples are power supply monitors, which reset the processor when a voltage is outside of its tolerance, and activity monitors, which reset the processor when the processor does not perform a prescribed sequence. **Reset Structure:** the architectural details of the various signals that stop execution of an ongoing process, or software application and restarts the processor at a known state. **Central Processing Unit (CPU) Throughput:** a measure of the number of processor instructions performed by the CPU per unit of time. (7) Power Supply Terms **Hold-up Capacity:** the capacity of the power supply to continue supplying output current after the input voltage drops below the minimum level. This is usually expressed as the time from the input voltage drop to the reset generated by the power supply. **Input Voltage & Current:** the input voltage is specified as nominal and acceptable variation values. The input current is specified as maximum steady state current. For the peak current, please see the term ‘Maximum Start-up (Inrush) Current Rating’ below. **Maximum Start-up (Inrush) Current Rating:** the maximum input current when the power supply first becomes active as a result of the input voltage increase to the minimum level. **Output Current Capacity:** the continuously operating maximum current supplied for each output voltage. **Power Monitors & Status Outputs:** separate circuitry which checks the output voltage levels and current loading of the power supply. This circuitry will generate one or more binary signals that may be connected to the processor to alert it to the ‘out of spec’ condition. These binary signals may also force the power supply to shut down to prevent damage to power supply components. **Power Resets:** a binary signal output from the power supply that is asserted when the output voltages are outside acceptable tolerances. **Regulation:** the percentage of variation of the output voltages when subjected to changes in load, changes in temperature, and all input voltage transients and deviations. **Restart:** the ability of the power supply or other circuit to return to the normal operating mode when the input voltage returns to or above the minimum level or when the tripped monitor indicates that the ‘out-of-spec’ condition has ended and the operating condition is returned to normal. **Short Circuit Management:** the circuitry that monitors for short circuits or overcurrent conditions in the power supply outputs. The results from this circuitry may shut down the affected output or the entire power supply. **Transient Immunity:** the ability of the power supply to continue operating normally during variations in the input voltage. This is usually expressed as the length of time and voltage level of the transient. **Voltage Outputs & Tolerances:** the voltage levels and tolerances of the outputs produced by the power supply. (8) Digital Communication Terms **Data Rates:** the number of data bits transmitted in a time period. This is usually expressed in thousands of bits per second (Kbps) or millions of bits per second (Mbps). **Integrity Checks:** the process that uses additional data accompanying the message information to validate that the message data was received without corruption or contamination. Examples are parity checks, checksums, data validity checks, and cyclic redundancy checks. **Maximum Bit Error Rates:** the largest number of bit errors allowed in a message transmission before the receiver invalidates its ability to receive data from that source. **Monitors:** separate circuitry that checks either the continuing operation of a transmitter, or that the receiver responds to input data. This circuitry will generate one or more binary signals that may be connected to the processor, alerting it to the ‘failed’ condition. **Resets:** conditions that result in the receiver or transmitter stopping operation, clearing all data, and restarting. **Signal Levels:** the minimum and maximum voltages for each state of the input or output. Typically, tolerances, thresholds, and the reference ground point are also identified. **Signal Rise and Fall Times:** the signal rise time is the time for the output to transition from 10 % to 90 % of the amplitude. The signal fall time is the time for the output to transition from the 90 % to the 10 % level. **Stub Length Limits:** the minimum and maximum length requirements of the wiring connector from the main bus to the inputs of the element. **3. Verification requirements** CO.cc) Each requirement shall be verified. CO.dd) Each characterisation item of IMA modules and functions, their associated attributes, their configurability and their performances shall be verified commensurately to the Development Assurance Level. CO.ee) Each characterisation item of the IMA module shall be verified over the usage domain. CO.ff) A set of verification procedures to demonstrate the compliance of the IMA module with the applicable MPS shall be developed and proposed as part of the certification data package. CO.gg) There is a distinction between demonstrating the capability of sharing and demonstrating the performance of that sharing function. When demonstrating the performance of the IMA module, a subset of the characterisation items that allows the behaviour of the complete IMA module during environmental testing shall be defined and submitted together with the Qualification Test Plan. Note that this functional subset should be detailed enough to sufficiently cover the performance of the complete IMA module. **4. Test Software representativeness** When embedded software is needed to test the IMA module, this module is authorised without the functional software (hosted applications) being installed and operating. CO.hh) Engineering analysis performed by the design holder shall determine that the test software (not the target functional software) is representative of the overall usage domain envelope of the module and related to the verification procedures. **5. Verification procedures** The following table provides verification methods for each requirement; nevertheless, an alternative method may be proposed to the certification authority. <table bgcolor="#d9d9d9" cellpadding="7" cellspacing="0"> <col/> <col/> <col/> <col/> <col/> <thead> <tr valign="top"> <td bgcolor="#808080"><p align="left"> Requirement identifier</p> </td> <td bgcolor="#808080"><p align="left"> Verification method</p> </td> <td bgcolor="#808080"><p align="left"> Test under normal conditions</p> </td> <td bgcolor="#808080"><p align="left"> Test Functional Subset(1) under environmental conditions</p> </td> <td bgcolor="#808080"><p align="left"> Comment</p> </td> </tr> </thead> <tbody> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.a)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.b)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.c)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.d)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.e)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.f)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.g)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.h)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.i)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> Reserved</p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.j)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.k)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.l)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.m)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.n)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.o)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y⁽²⁾</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.p)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.q)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.r)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.s)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.t)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.u)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I+A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.v)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I+A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.w)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I+A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.x)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.y)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.z)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.aa)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.bb)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.cc)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> I+A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.dd)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.ee)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> T(A*)</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> Y</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.ff)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.gg)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> <tr valign="top"> <td bgcolor="#d9d9d9"><p align="center"> <b>CO.hh)</b></p> </td> <td bgcolor="#d9d9d9"><p align="center"> A</p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> <td bgcolor="#d9d9d9"><p align="center"> <br/> </p> </td> </tr> </tbody> </table> ***Table 1: Verification Acceptance Criteria*** (A\*) means that verification by the Analysis method is possible for items that cannot be tested. Note (1): applicable for a functional subset as defined in CO.gg). Note (2): the Usage Domain has to be taken into consideration during Environmental Qualification Testing in order to evaluate the robustness of the IMA module over the full Usage Domain (see Appendix 4, Chapter 1). [Amdt ETSO/10] [Amdt ETSO/16]